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作者(中文):賴彥廷
論文名稱(中文):乒乓網格:一個高效的時脈網格設計
論文名稱(外文):Ping-Pong Mesh: An Efficient Clock Mesh Design
指導教授(中文):張世杰
口試委員(中文):黃世旭
王廷基
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:101062609
出版年(民國):103
畢業學年度:102
語文別:英文
論文頁數:36
中文關鍵詞:時脈網格
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隨著製程技術越來越進步,晶片變異(on-chip-variation, OCV)的影響已經佔了時脈偏移(clock skew)相當大的比例,而限制了晶片的效能。為了解決晶片變異的問題,時脈網格(clock mesh)的架構被廣泛的應用在許多高效能的設計上。不幸的是,時脈網格的架構會產生非常大的能量消耗以及瞬間電流。因此,近年來提出了共振時脈(resonant clock)的方法來減少能量消耗問題。然而,先前的方法需要加入大量的去耦電容(decoupling capacitors),最後的結果常受限於面積成本。在本文中,我們提出了一個創新的時脈共振架構,稱為乒乓網格(Ping-Pong mesh),來克服那些缺點。我們的兵乓網格架構包含了兩個子網格,分別扮演另一個子網格的去耦電容,且兩個子網格運作在完全相反的時脈相位。我們的兵乓網格有以下兩個優點:(1)兵乓網格不像先前的架構需要額外的去耦電容;(2)相較於先前的架構,兵乓網格能夠減少大約一半的瞬間電流。
List of Contents
List of Contents VI
List of Figures VII
List of Tables VIII
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PRELIMINARIES 6
CHAPTER 3 IDEAL LC MODEL FOR PING-PONG MESH 8
CHAPTER 4 PING-PONG MESH DESIGN 13
4.1 Mesh Architecture Design 13
4.2 Inductor Implementation 15
4.3 Optimal Inductor Estimation 17
4.4 Inductor Placement 20
CHAPTER 5 EXPERIMENTAL RESULTS 24
CHAPTER 6 CONCLUSIONS 33
REFERENCES 34
[1] S. C. Chan, K. Shepard, and P. Restle, "Design of resonant global clock distributions,” in Proc. ICCD, pp. 248-253, 2003.
[2] S. C. Chan, et al., "A Resonant Global Clock Distribution for the Cell Broadband Engine Processor," in IEEE Journal of Solid-State Circuits, pp.64-72, 2009.
[3] S. C. Chan, P. Restle, K. Shepard, N. James, and R. Franch, "A 4.6 GHz resonant global clock distribution network," in Proc. ISSCC, pp. 342–343, 2004,.
[4] V. Chi, "Salphasic distribution of clock signals for synchronous systems," in IEEE Trans. Comput., vol. 43, no. 5, pp. 597–602, May 1994.
[5] M. Desai, R. Cvijetic, and J. Jensen, "Sizing of clock distribution networks for high performance CPU chips, " in Design Automation Conference, pp. 389–394, 1996.
[6] A. Drake, K. Nowka, T. Nguyen, J. Burns, and R. Brown, "Resonant clocking using distributed parasitic capacitance," in IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1520–1528, Sep. 2004.
[7] M. R. Guthaus, G. Wilke, and R. Reis, "Non-uniform clock mesh optimization with linear programming buffer insertion," in Design Automation Conference, 2010.
[8] X. Hu and M. Guthaus. "Distributed LC resonant clock grid synthesis," in IEEE Transactions on Circuits and Systems I (TCAS-I), pp. 2749-2760, 2012.
[9] M. Mori, H. Chen, B. Yao, and C. K. Cheng, "A multiple level network approach for clock skew minimization with process variations," in Asia and South Pacific Design Automation Conference, pp. 263-268, 2004.
[10] A. M. Niknejad, "ASITIC: Analysis of Si Inductors and Transformers for ICs," http://rfic.eecs.berkeley.edu/~niknejad/doc-05-26-02/asitic.html
[11] M. M. Ozdal, C. Amin, A. Ayupov, S. Burns, G. Wilke, C. Zhuo, "The ISPD -2012 Discrete Cell Sizing Contest and Benchmark Suite," in Proc. ACM International Symposium on Physical Design, pp. 161-164, 2012.
[12] F. O’Mahony, C. Yue, M. Horowitz, and S.Wong, "Design of a 10GHz clock distribution network using coupled standing-wave oscillators, " in Proc. DAC, pp. 682–687, 2003.
[13] A. Rajaram and D. Z. Pan, "MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1945-1958, Dec. 2010.
[14] P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, and A. Mule, "The clock distribution of the POWER4 microprocessor," in ISSCC, pages 144–145, 2002.
[15] V. Sathe, S. Arekapudi, C. Ouyang, M. Papaefthymiou, A. Ishii, and S. Naffziger,"Resonant clock design for a power-efficient high-volume x86-64 microprocessor," in IEEE International Solid-State Circuits Conference, pp. 68-70, 2012.
[16] B. Taskin, J. Demaio, O. Farell, M. Hazeltine, and R. Ketner, "Custom topology rotary clock router with tree subnetworks," in Trans. Design Automation Electron. Syst., vol. 14, no. 3, May 2009.
[17] G. Venkataraman, Z. Feng, J. Hu, and P. Li, "Combinatorial algorithms for fast clock mesh optimization, " in International Conference on Computer-Aided Design, pp 563-567, 2006.
[18] J.Wood, T. C. Edwards, and S. Lipa, "Rotary traveling-wave oscillator arrays: A new clock technology, " in IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1654–1664, Nov. 2001.
[19] L. Xiao, Z. Xiao, Z. Qian, Y. Jiang, T. Huang, H. Tian, and F.-Y. Young, "Local clock skew minimization using blockage-aware mixed treemesh clock network," in Proc. International Conference on Computer-Aided Design, pp. 458-462, 2010.
[20] C. Yeh et al., "Clock Distribution Architectures: a Comparative Study," in Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 85-91, 2006.
[21] Z. Yu and X. Liu, "Implementing multiphase resonant clocking on a finite-impulse response filter, " in IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 11, pp. 1593–1601, Nov. 2009.
[22] C. Ziesler, S. Kim, and M. Papaefthymiou, "A resonant clock generator for single-phase adiabatic systems, " in Proc. ISLPED, 2001.
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